The present invention relates generally to semiconductor devices and, more particularly, to trench isolation process technology for use in memory, image, logic and other semiconductor devices.
Implementing electronic circuits involves connecting isolated devices or circuit components through specific electronic paths. In silicon integrated circuit (IC) fabrication, it is necessary to isolate devices that are formed in a single substrate from one another. The individual devices or circuit components subsequently are interconnected to create a specific circuit configuration.
As the density of the devices continues to rise, parasitic inter-device currents become more problematic. Isolation technology, therefore, has become a critical aspect of integrated circuit fabrication.
For example, dynamic random access memory (DRAM) devices generally comprise an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Each memory cell in a DRAM stores one bit of data and consists of one transistor and one capacitor. Within the array, each memory cell must be electrically isolated from adjacent memory cells. The degree to which large numbers of memory cells can be integrated into a single IC chip depends, among other things, on the degree of isolation between the memory cells.
Similarly, in metal-oxide-semiconductor (MOS) technology, isolation must be provided between adjacent devices, such as NMOS or PMOS transistors or CMOS circuits, to prevent parasitic channel formation. CMOS circuits can be used, for example, to form the pixels in a photosensitive imaging device and must be isolated from one another. In the case of CCD or CMOS imagers which are intentionally fabricated to be sensitive to light, it is advantageous to provide both electrical and optical isolation between pixels.
Shallow trench isolation (STI) is one technique which can be used to isolate devices such as memory cells or pixels from one another. In general, a trench is etched into the substrate to provide a physical barrier between adjacent devices. Refilled trench structures, for example, consist essentially of a sub-micron recess formed in the silicon substrate by a dry anisotropic or other etching process. The recess is filled with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO2). The filled trench then is planarized by an etchback process so that the dielectric remains only in the trench and its top surface level with that of the silicon substrate.
Refilled trench isolation is sometimes categorized according to the dimensions of the trench: shallow trenches (less than about 1 micron), moderate depth trenches (1–3 microns), and deep narrow trenches (greater than 3 microns deep, less than 2 microns wide). Shallow trench isolation is used, for example, to isolate devices.
To enhance the isolation further, ions can be implanted in the silicon substrate in the area directly beneath the trench. However, as noted, for example, in S. Nag et al., “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 μm Technologies,” IEEE IEDM, pp. 841–844 (1996), some ion implants can result in high current leakage. In particular, when ions are implanted in the substrate close to the edges of the trench, current leakage can occur at the junction between the active device regions and the trench. Similarly, if the trench is shallow, then a photon impinging on a particular pixel of a photosensitive device may diffuse under the trench isolation structure to an adjacent pixel, resulting in detection of the photon by the wrong pixel. Accordingly, it is desirable to improve the trench isolation techniques to address those and similar problems.